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A simple method for separation of the intrinsic and peripheral junction capacitances in bipolar transistors

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2 Author(s)
M. Jo ; Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA ; D. E. Burk

A simple technique for extracting the intrinsic and peripheral capacitances from measurements on transistors that are fabricated in the same process but have different emitter areas is presented. The technique has the advantage that no calibration is needed to remove the contact pad and other parasitic capacitances from the measured data. A three-step approach for extracting the zero-bias intrinsic and peripheral junction capacitances, the built-in potential and power dependence for the equivalent bias-dependent capacitances, and the corner capacitance of the peripheral transistor and the parasitic capacitance using transistors with different emitter areas is outlined. The underlying assumptions in this approach are given. The accuracy of the technique is verified by simulations of junction capacitance as a function of bias for individual transistors

Published in:

IEEE Transactions on Electron Devices  (Volume:37 ,  Issue: 1 )