Referenced Items are not available for this document.
Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.
Published in:
Communications, IEEE Transactions on
(Volume:55
,
Issue:
11
)
Date of Publication: Nov. 2007
- Page(s):
- 2084 - 2091
- ISSN :
- 0090-6778
- INSPEC Accession Number:
- 9675435
- Digital Object Identifier :
- 10.1109/TCOMM.2007.908517
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 12 November 2007
- Issue Date :
- Nov. 2007
- Sponsored by :
- IEEE Communications Society
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