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Generic Description and Synthesis of LDPC Decoders

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4 Author(s)
FrÉdÉric Guilloud ; GET/Ecole Nat. Superieure des Telecommun. Bretagne, Brest ; Emmanuel Boutillon ; Jacky Tousch ; Jean-Luc Danger

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.

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IEEE Transactions on Communications  (Volume:55 ,  Issue: 11 )