By Topic

Generic Description and Synthesis of LDPC Decoders

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Guilloud, F. ; GET/Ecole Nat. Superieure des Telecommun. Bretagne, Brest ; Boutillon, E. ; Tousch, J. ; Danger, J.-L.

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.

Published in:

Communications, IEEE Transactions on  (Volume:55 ,  Issue: 11 )