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Double-gate MOS (DGMOS) technologies are emerging as possible substitutes for single-gate planar bulk devices in the near future. This paper defines and presents different DGMOS device-and circuit-design possibilities. It studies Schmitt triggers to eloquently analyze the interplay between noise immunity, circuit speed, and power dissipation as a function of device-level parameters. The asymmetric DGMOS devices and independent-gate technology can provide high noise immunity and dynamic power reduction at increased gate-delay, leakage-power, and process-sensitivity penalties. Furthermore, connected-gate DGMOS circuits work best with symmetric devices.