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Architecture of A Wavelet Packet Transform Using Parallel Filters

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2 Author(s)
Mohsen Amiri Farahani ; Ms-student at Electrical and Computer engineering faculty, Shahid Beheshti University, Tehran, Iran, E-mail: m ; Mohammad Eshghi

In this paper, based on the word-serial pipeline architecture and parallel filter processing, a new architecture for direct and inverse wavelet packet transforms is introduced. This architecture increase the speed of the wavelet packet transforms. In this design a word-serial architecture able to compute a complete wavelet packet transform (WPT) binary tree in an on-line fashion, but easily configurable in order to compute any required WPT sub tree, is proposed. In this architecture, a high-pass filter and a low-pass filter are used concurrently, in order to compute the new coefficients. This architecture is suitable for the high speed on-line applications. With this architecture, the speed of the wavelet packet transforms is increased with a factor 2, but the occupied area of the circuit is less than double. This architecture can be applied to any levels tree structure with any filter coefficients length.

Published in:

Applied Electronics, 2006. AE 2006. International Conference on

Date of Conference:

6-7 Sept. 2006