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A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With −75 dBc Single-Tone Sensitivity at 100 kHz Offset

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3 Author(s)
Khalil, W. ; Intel Corp., Chandler ; Bakkaloglu, B. ; Kiaei, S.

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 12 )

Date of Publication:

Dec. 2007

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