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An Integrated Ultra-Wideband Timed Array Receiver in 0.13 μm CMOS Using a Path-Sharing True Time Delay Architecture

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3 Author(s)
Ta-Shun Chu ; Univ. of Southern California, Los Angeles ; Roderick, J. ; Hashemi, H.

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 mum CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 12 )

Date of Publication:

Dec. 2007

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