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A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

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2 Author(s)
Brooks, L. ; Massachusetts Inst. of Technol., Cambridge ; Hae-Seung Lee

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 12 )

Date of Publication:

Dec. 2007

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