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A significant challenge in designing algorithms for FPGA-based reconfigurable computers is the exposed, non-cached memory subsystem. In the absence of dedicated hardware to manage a cached memory hierarchy, the algorithm designer must explicitly allocate data within a collection of memory banks, and schedule access to the memories in the algorithm's datapaths. The physical location in memory affects the datapath schedule, yet data dependencies in the algorithm can suggest allocation strategies to increase instruction level parallelism. In this work, we present three algorithms that automatically allocate arrays to memory banks and schedule datapaths that use those memories. Our algorithm allows the user to trade-off optimal results versus longer iterative analysis.