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An FPGA Based Memory Efficient Shared Buffer Implementation

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6 Author(s)
Burns, D. ; Queen''s Univ. Belfast, Belfast ; Toal, C. ; McLaughlin, K. ; Sezer, S.
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This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.

Published in:

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Date of Conference:

27-29 Aug. 2007