Skip to Main Content
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.
Date of Conference: 27-29 Aug. 2007