Referenced Items are not available for this document.
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.
Published in:
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Date of Conference: 27-29 Aug. 2007
- Page(s):
- 661 - 664
- E-ISBN :
- 978-1-4244-1060-6
- Print ISBN:
- 978-1-4244-1060-6
- INSPEC Accession Number:
- 9792493
- Conference Location :
- Amsterdam
- Digital Object Identifier :
- 10.1109/FPL.2007.4380740
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
