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A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the field programmable gate array (FPGA) has not yet been established. Current work in automatic task partitioning and scheduling for the reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this research, we consider the problem of formalizing a co-scheduling methodology and develop a set of intuitive tools to assist users in realizing the full potential of an RC architecture. Scheduling is critical for efficient resource utilization and achieving speedup in high performance reconfigurable computers (HPRC). The primary targets of this research are reconfigurable computing (RC) systems that have both microprocessors and FPGAs.