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Implementation on FPGA of a LUT-Based atan(Y/X) Operator Suitable for Synchronization Algorithms

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2 Author(s)
Gutierrez, R. ; Miguel Hernandez Univ., Elche ; Valls, J.

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC with the same latency.

Published in:

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Date of Conference:

27-29 Aug. 2007