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Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration

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2 Author(s)
Noguera, J. ; Xilinx Res. Labs, Dublin ; Kennedy, I.O.

We introduce a new approach to reducing FPGA power consumption. By exploiting the time varying nature of a systems environment, we are able to extract power consumption savings. We do this by closely tracking environmental changes and adapting the implementation accordingly using partial reconfiguration. We chose network infrastructure equipment to provide the context for the work since it is a significant consumer of FPGAs and is deployed in diverse environments. The network industry is also very interested in reducing FPGA power consumption as part of a major system wide effort, since it faces regulatory pressure, environmental concerns and rising electricity bills. We present a new experimental framework for measuring the power consumption of FPGA cores. The framework is used in an illustrative case study of how the approach works with a Viterbi decoder. The experiments give encouraging results and show that significant savings in power consumption can be obtained.

Published in:

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Date of Conference:

27-29 Aug. 2007