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Adventures with a Reconfigurable Research Platform

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1 Author(s)
Wawrzynek, J. ; Univ. of California, Berkeley

The computer industry is at a cross-roads. The problems associated with scaling uniprocessor performance has forced all major computer manufactures to turn to multi-and many-core architectures. This sea change in processor design has created many opportunities for field programmable logic. In the RAMP project, we are developing an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to caches to networks, is implemented in FPGAs for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, assembled and run. By using hardware rather than simulation, RAMP will be fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP will run full, unmodified software stacks. RAMP's intended audience includes anyone designing and using multiprocessor systems, including architecture researchers, software developers, and end users. In this talk, I will describe the background and current state of the RAMP development and related projects using our FPGA platform, the Berkeley emulation engine (BEE).

Published in:

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Date of Conference:

27-29 Aug. 2007