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Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

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3 Author(s)
Pugliese, A. ; Calabria Univ., Rende ; Cappuccino, G. ; Cocorullo, G.

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 1 )

Date of Publication:

Jan. 2008

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