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We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited; 2) the decoder circuit critical path may be greatly reduced; and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.