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Use of Low-Density Parity-Check Codes for Dominant Error Events Detection and k -Constraint Enforcement

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2 Author(s)
Fei Sun ; Marvell Semicond., Santa Clara ; Tong Zhang

In this paper, we propose to leverage the simple and explicit parity checks inherent in low-density parity-check (LDPC) codes to detect dominant error events without code rate penalty. This is enabled by enforcing a very weak constraint on the LDPC code parity check matrix structure. Such a constraint can be readily satisfied by most structured LDPC codes reported in the open literature, such as quasi-cyclic (QC) LDPC codes. Moreover, this zero-redundancy dominant error events detection can be extended to handle the bit errors that occur when deliberate bit-flipping is used to enforce -constraints. We have demonstrated the effectiveness of the proposed method in computer simulations.

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Magnetics, IEEE Transactions on  (Volume:43 ,  Issue: 12 )