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Architecture of the Scalable Communications Core's Network on Chip

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4 Author(s)
David Arditti Ilitzky ; Intel''s Commun. Res. Center, Guadalajara ; Jeffrey D. Hoffman ; Anthony Chun ; Brando Perez Esparza

The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.

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IEEE Micro  (Volume:27 ,  Issue: 5 )