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On-Chip Interconnection Networks of the TRIPS Chip

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7 Author(s)
Gratz, P. ; Univ. of Texas at Austin, Austin ; Changkyu Kim ; Sankaralingam, K. ; Hanson, H.
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The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

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Micro, IEEE  (Volume:27 ,  Issue: 5 )