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Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. Based on a programming model for massively parallel embedded computing that is reasonable and productive for software developers, we developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC. This MPPA's architecture is based on the structural object programming model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.