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On-chip network design has become an increasingly important component of computer architecture. the cell broadband engine's element interconnect bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on- chip networks. to help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the ElB network using conventional latency and throughput characterization methods.
Date of Publication: Sept.-Oct. 2007