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Debug architecture for the En-II system chip

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2 Author(s)
Vermeulen, B. ; Corp. I&T/Res., Eindhoven ; Bakker, S.

A comprehensive system debug methodology is presented, which combines the state-of-the-art support for software, functional hardware and process technology debug. The application of this methodology to the 65-nm CMOS En-II SoC is described, containing among others a high-performance ARM CPU and a TriMedia VLIW DSP. The debug requirements and implementation choices made are explained in detail.

Published in:

Computers & Digital Techniques, IET  (Volume:1 ,  Issue: 6 )