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A New Finite-Field Multiplier Using Redundant Representation

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3 Author(s)
Namin, A.H. ; Univ. of Windsor, Windsor ; Huapeng Wu ; Ahmadi, M.

A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower complexity and comparable critical path delay or a significantly smaller critical path delay and comparable complexity in comparison to the previously proposed architectures using the same representation. For the class of fields where there exists a type I optimal normal basis, the proposed multiplier compares favorably to the normal basis multipliers. A digit-level version for the new multiplier is also presented in this paper.

Published in:

Computers, IEEE Transactions on  (Volume:57 ,  Issue: 5 )

Date of Publication:

May 2008

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