Skip to Main Content
This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. The size of the control LFSR, which is determined by the number of specified bits in the most specified control pattern, is minimized by propagating only one fault effect for each fault and targeting the faults that are uniquely detected by each test pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Very high compression (over 230X) is achieved for benchmark and industrial circuits by the proposed method. Experimental results show that the sizes of control data for the proposed method are smaller than prior work and the runtime of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.