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Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

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6 Author(s)
Matthias Hartmann ; Department of Electrical Engineering, University of Technology Dresden, Helmholtzstrasse 18, 01062 Dresden, Germany ; Vassilis Pantazis ; Tom Vander Aa ; Mladen Berekovic
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Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigate the mapping of two image processing algorithms, wavelet encoding and decoding, and TIFF compression on this novel type of array architectures in a systematic way. The results of our experiments show that CGRAs based on ADRES and its DRESC compiler technology deliver improved performance levels for these two benchmark applications when compared to results obtained on a state-of-the art commercial DSP platform, the c64times DSP from Texas Instruments. ADRES/DRESC can beat its performance by at least 50% in cycle count and the power consumption even drops to 10% of the published numbers of the c64times DSP.

Published in:

2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

Date of Conference:

4-5 Oct. 2007