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Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories

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3 Author(s)

This paper proposes a code placement algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a noncacheable memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm simultaneously finds code layouts for a cacheable region, a scratchpad region, and the other non-cacheable region of the address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23% without any performance loss compared to the best result achieved by the conventional approach.

Published in:

Embedded Systems for Real-Time Multimedia, 2007. ESTIMedia 2007. IEEE/ACM/IFIP Workshop on

Date of Conference:

4-5 Oct. 2007

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