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Implementation of multi-layer leaky integrator networks on a cellular processor array

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4 Author(s)
Barr, D.R.W. ; Manchester Univ., Manchester ; Dudek, P. ; Chambers, J.M. ; Gurney, K.

We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motivated by existing biologically plausible models of a set of sub-cortical nuclei -the basal ganglia. The model includes 5 layers, each consisting of 16384 leaky integrator neurons, with inter-layer synaptic weights forming various one-to-one and diffuse connectivity patterns. The architecture of the SIMD processor array allows all the neurons per layer to be updated simultaneously. The performance of the processor array chip in simulating the model is compared with the original model being executed on a computer workstation. It is demonstrated that in this application the chip outperforms the workstation by five orders of magnitude in terms of computational performance and seven orders of magnitude in terms of energy efficiency, providing a high-speed, low-power, compact hardware platform for possible embedded robotic applications.

Published in:

Neural Networks, 2007. IJCNN 2007. International Joint Conference on

Date of Conference:

12-17 Aug. 2007