A structured methodology for IC photolithography synthesis in semiconductor manufacturing

A simple method for structuring the synthesis of an integrated-circuit photolithography fabrication process is described. This method has allowed Cameo, a computer-aided photolithography process synthesis system, to be built. Cameo is useful for synthesizing and evaluating a number of possible good solutions to a set of photolithography process requirements. In its current prototype implementation it is most useful for users who are familiar with integrated-circuit photolithography but are not experts. The structuring mechanism is based on dividing photolithography process design into three main subtasks corresponding to initial strategic decisions: choosing the aligner/exposer, choosing the photoresist and scheme for its application, and choosing the etch method. The synthesis work proceeds in turn at three distinct levels of detail in each subtask, the last level resulting in the complete fabrication recipe. Four types of solution methods were found to suffice for implementing nearly all steps of the synthesis: rule-based reasoning, algorithmic computation, graph interpolation, and table lookup.<
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