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A 3.3-V CMOS technology with 0.6- mu m design rules in sixth-generation twin-tub CMOS (twin-tub VI) was developed. The major features of the device in this technology are: HIPOX twin-tub structure, n+/p+ dual-type poly gate, 125-AA thin gate oxide, shallow junctions, rapid thermal anneal activation, and thin TiSi2 as the source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latchup immunity for 4.5- mu m n+-to-p+ spacing, more than 6.0-V NMOSFET snapback breakdown voltage, good hot-carrier aging properties, and undetectable dopant interlateral diffusion through a TiSi2 shunt layer of a different type of poly. The transistors were scaled to 0.45- and 0.40- mu m effective channel length without punchthrough at Vds=3.6 V for NMOS and PMOS, respectively. A 100-ps stage delay was obtained on a 101-stage CMOS ring oscillator at an operating voltage of 3.3 V.