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A bipolar-mode multibit soft-error mechanism in static random-access memory (SRAM) devices has been explored by utilizing a 3D device simulation of an inverter constructed with a driver n-MOSFET, a load resistor, and capacitors. Generally, a well tap was not set at every SRAM unit cell so as to increase the packing density. We have introduced a model structure where a p-well for arranging the driver n-MOSFET in a CMOS inverter does not have the well tap in the analyzed cell, and we have studied the inverter action when a drain junction of the n-MOSFET in an OFF-state is hit by an alpha -particle. We found that the p-well is forwardly biased by generated excess carriers. The forward bias at the p-well switches the n-MOSFET from the OFF-to the ON-state, like an on action of an n-p-n transistor, and the output potential of the inverter changes from high to low. This bias change results in a flip on the state of the SRAM unit cell. When a series of n-MOSFETs (or p-MOSFETs) is arranged in the same well and the well tap is not arranged in every unit cell, the switch-on action of the MOSFET is sequentially induced, like a chain reaction. We have developed a multidrain model by adding a p-n junction around the n-MOSFET in the p-well and have successfully demonstrated the chain reaction. In addition, we have demonstrated the soft-error occurrence in an unit cell with the help of circuit simulation. This is the mechanism of multiple soft errors by the bipolar-mode operation. A key factor for evaluating the tolerance of the bipolar-mode soft error is a forwardly biased time at the well (i.e., a well-floating time). The well-floating time (tfloat) is dependent on an initial charge (Qi) in the depletion layer and a resistance (-Rwell) between the well and the tap. The tfloat has been precisely analyzed as functions of Qi and -Rwell, and a critical charge, defined by Qi over which the memory state is fli- pped, has been clarified for single-and two-bit errors.