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Notice of Violation of IEEE Publication Principles
"A Low Reference Spurs 15 GHz 0.13 μm CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter Architecture"
by Maxim, A.
in the IEEE Journal of Solid-State Circuits,
Volume 42, Issue 11, Nov. 2007 Page(s):2503 - 2514
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A wide tuning range, low phase noise and spurs, multi-gigahertz frequency synthesizer was realized in 0.13 mum CMOS using a fully-sampled feed-forward loop filter. Both the integral and proportional loop filter paths use sample and hold switched-capacitor networks that completely isolate the oscillator from the charge-pump switching transients. The sampled nature of the filter, together with a digital domain implementation of the ripple-filtering pole spread the impulsive energy coming from the charge-pump current injection over several reference clock cycles, resulting in a dramatic reduction of the oscil- ator control signal ripple and thus a very low reference spur level. A multi-regulator PLL architecture reduces the supply injected noise and spurious tones, allowing the integration of the synthesizer on the same die with a large digital core, as required by modern single-chip receiver SoCs. PLL specifications include: < 1deg rms double-sided integrated phase noise from 1 kHz to 10 MHz, -85 dBc reference spurs, < -80 dBc supply injected spurs, 300 times 750 mum2 die area and < 100 mW power dissipation from a single 2.5 V supply.