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A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (109 multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between the LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256 times 512 array of 3-T charge-conserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated in a face detection task.