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The spirit of system-on-chip (SoC) approach is to integrate more and more system functions into one single chip. Consequently, the on-chip clock requirement could be very complicated due to the various functions the chip has to support. To fulfill those clock needs, it is not uncommon for more than several phase-locked loop (PLLs) to be used within one such large chip. Designing these on-chip PLLs is a very challenging task in term of cost and performance. To solve this problem for a HDTV SoC of over 50 millions transistors, a ldquoflying-adderrdquo architecture based PLL (FAPLL) is constructed. This generic FAPLL is instantiated multiple times in this SoC for different functions, resulting in significant chip cost reduction.