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The parametrically coupled logistic map network (PCLMN) can serve as the front-end dynamic neural network (DNNs) for clustering and generation of spatio-temporal patterns. In this brief, the element of the PCLMN is designed in a 0.25-mum 2.5-V CMOS process for low power consumption. The analog design employs self-calibration techniques to improve the accuracy of the low-power element. After calibration, the fabricated element is able to generate a 1-D map and the nonlinear interconnection in 4-bit resolution for driving signals up to 1 MHz, with a power consumption of 12 mW.