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Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits

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2 Author(s)
Pomeranz, I. ; Purdue Univ., West Lafayette ; Reddy, S.M.

We describe a method for on-line testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semi-concurrent on-line testing. While unknown input vectors are applied to the circuit that participates in useful computations, the proposed method applies modified vectors to the idle circuit. In this way, different conditions are created for the detection of delay faults, allowing identical delay faults that affect both circuits to be detected. In designing the modified vectors, we ensure that the expected fault free responses of the two circuits are identical. We also ensure that the hardware for modifying the vectors applied to the idle circuit will be easy to implement on-chip.

Published in:

Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on

Date of Conference:

26-28 Sept. 2007

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