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Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing

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3 Author(s)
Ikeda, T. ; Chiba Univ., Chiba ; Namba, K. ; Ito, H.

In recent high-density, high-speed and low-power VLSIs, soft errors (SEs) and delay faults (DFs) frequently occur. Therefore, SE hardened design and DF testing are essential. This paper proposes three types of scan flip-flops (FFs) which have SE tolerant capability and allow enhanced scan shifting for DF testing, i.e. arbitrary two-pattern testing. The slave latches used in these FFs are constructed by adding some extra transistors which make enhanced scan shifting possible for DF testing on an existing SE hardened latch. The areas and time overheads of the proposed latches are up to 33.3% and 31.4% larger than those of the existing SE hardened latch respectively. However, the areas of the proposed FFs are about 30% smaller than existing FFs which have SE tolerant capability and allow enhanced scan shifting for DF testing.

Published in:

Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on

Date of Conference:

26-28 Sept. 2007