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A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance

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5 Author(s)
Srivastava, A. ; Univ. of Michigan, Ann Arbor, MI ; Chopra, K. ; Shah, S. ; Sylvester, D.
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Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, by finding their joint probability distribution function. We consider inter-die variations, as well as intra-die variations, with correlated and random components. The correlation between power and performance arises due to their dependence on common process parameters and is shown to have a significant impact on the yield, particularly in high-frequency bins. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizing and gate-length biasing in the circuit with high efficiency and accuracy. We show how this gradient information can be effectively used by a nonlinear optimizer to perform yield optimization. The proposed yield-analysis approach is compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%. The proposed optimization approach is implemented and tested, and we demonstrate an average yield increase of 40% using gate sizing (as compared to a deterministically optimized circuit). Even higher improvements are demonstrated when both gate sizing and gate-length-biasing techniques are used.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:27 ,  Issue: 2 )