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Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks

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1 Author(s)
Sanghyeon Baeg ; Hanyang Univ., Kyeonggi

Testing for delay faults in heavily gated clock designs has the major test challenges of reduced fault coverage and high test power consumption. In the scan-test method, gated clocks are often simplified and replaced with global test clocks. As such, partial clocking by the gated clocks is not inherited in test operations. Global clocking suffers from delay fault coverage loss because a sensitization state cannot easily be created due to the increased state dependence in functional paths, as compared to partial clocking. The global clocking scheme in the test mode is not adequate for low-power designs either, because the power consumed during a test operation exceeds that used during a normal operation. The power grid may not be sufficient to support the power drawn during testing, perhaps resulting in overkilled devices. It is therefore critical that power consumption be maintained under a safe limit, even during testing. In the proposed method, partial clocking in gated designs is preserved to the maximum possible to create more reachable states, thereby increasing transition fault coverage and reducing test power during launch and capture cycles. A transition fault simulator was developed, and it demonstrated higher transition fault coverage and reduced test power for ISCAS-89 circuits when partial clocking is used.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:26 ,  Issue: 12 )