By Topic

Analytical Solutions for Interconnect Stress in Board Level Drop Impact

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

Closed form analytical solutions for the stresses in the interconnects between the integrated circuit (IC) package and the printed circuit board (PCB) when the PCB assembly is subjected to a mechanical shock have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnects when subjected to mechanical shock, and have been used to establish the following key findings: 1) for the same magnitude of strain measured on the PCB, symmetric bending will result in the highest stress in the interconnect while anti-symmetric bending will result in the least stress; 2) the cross-section area of the interconnect is the single most critical parameter; 3) the eight-layer buildup board specified in JEDEC standard JESD22-B111 can be replaced with an equivalent conventional board that exhibits similar natural frequency as the eight-layer buildup board.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:30 ,  Issue: 4 )