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A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip

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2 Author(s)
Xiang Xiao ; Indiana Univ., West Lafayette ; Jaehwan Lee

Given the projected dramatic increase in the number of processors and resources in a system-on-a-chip, a quadratic increase in the likelihood of deadlock is predicted due to complex system behavior. To deal with this issue, we here present a novel parallel hardware-oriented deadlock detection algorithm with O(l) deadlock detection and 0(min(m,n)) preparation, where m and n are the numbers of processes and resources, respectively. Our contributions are (i) the first O(l) deadlock detection hardware implementation and (ii) a new algorithmic method of achieving 0(min(m,n)) overall run-time complexity. We implement our algorithm in Verilog HDL and demonstrate that deadlock detection always takes only two clock cycles regardless of the size of a system (i.e., m and n).

Published in:

IEEE Computer Architecture Letters  (Volume:6 ,  Issue: 2 )