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Scaling Three-Dimensional SOI Integrated-Circuit Technology

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8 Author(s)
Chen, C.K. ; Massachusetts Inst. of Technol., Lexington ; Warner, K. ; Yost, D.R.W. ; Knecht, J.M.
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In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +/--0.5 mum wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a back-metal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.

Published in:

SOI Conference, 2007 IEEE International

Date of Conference:

1-4 Oct. 2007

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