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A Normalization Method for Arithmetic Data-Path Verification

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4 Author(s)
Wedler, M. ; Univ. of Kaiserslautern, Kaiserslautern ; Stoffel, D. ; Brinkmann, R. ; Kunz, W.

We propose a normalization technique for verifying arithmetic circuits in a bounded model-checking environment. Our technique operates on the arithmetic bit-level (ABL) description of the arithmetic circuit parts and property. The ABL description can easily be provided by the front-end of a register transfer level property checker. The proposed normalization greatly simplifies the SAT instances to be solved for arithmetic circuit verification. Our approach has been successfully applied to verify the integer pipeline of an industrial microprocessor with advanced DSP capabilities.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:26 ,  Issue: 11 )

Date of Publication:

Nov. 2007

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