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Nanoscale device characteristics and noise coupling have rendered traditional waveform-based gate delay models increasingly difficult to adopt. While the widely adopted delay models are built upon the assumption of simple ramp-like signal waveforms, realistic signal shapes in nanoscale designs can be far more complex. The need for considering process-voltage-temperature (PVT) variations imposes further accuracy requirement on gate models. We present a parameterizable waveform independent gate model (PWiM) where no assumption is made upon the input waveforms. The PWiM model is constructed by encapsulating the driver's intrinsic nonlinear dc and dynamic characteristics, which are important to model for complex signal waveforms, via novel and yet easy-to-implement characterization steps. As such, PWiM can provide near-SPICE accuracy for input signals that significantly deviate from simple ramps. While recently developed current-based models can only be applied to single channel-connected component, PWiM can work for multistage cells leading to improved library compactness and analysis efficiency. Our experiments have indicated that the proposed driver model not only provides up to two orders of magnitude speedups over SPICE for delay and noise analysis, it also offers accurate assessment of performance variability introduced by process and environmental variations.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:15 , Issue: 11 )
Date of Publication: Nov. 2007