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High-Voltage Low-Power Analog Design in Nanometer CMOS Technologies

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5 Author(s)

Higher level of integration, lower cost and higher speed are driving CMOS technology deeper into nanometer regime of 65 nm and below. To ensure reliability of these 65 nm devices, power supply is scaled down to 1.2 V. However, certain functions such as high-speed USB and audio CODEC require higher power supply voltages of 3.3 V and 2.1 V. The minimum supply voltage of CODEC is determined by the power that needs to be delivered to the speakers or maximum input signal voltage that needs to be processed. Higher supply voltage provides lower power consumption for many analog functions. In this paper, methods of high voltage analog circuit integration into a 65 nm mixed-signal system are discussed. These integration methods include system in package (SiP) and system on chip (SoC.) SiP offers a low cost and fast to market option for mixed analog/digital integration. In some cases, system on chip (SoC) is desired due to lower power dissipation. High voltage active RC and switched-capacitor circuit design techniques using thin-oxide or combination of thin-and thick-oxide transistors are presented.

Published in:

Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE

Date of Conference:

Sept. 30 2007-Oct. 2 2007