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Implementation of High-speed High-resolution Data Conversion System Using FPGA

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3 Author(s)
Cao Xiaoqiu ; Beijing Univ. of Technol., Beijing ; Zeng Jin ; Yang Tao

This paper analyzes the implementation of high-speed high-resolution data conversion system based on Subranging A/D model in detail. We use a 10 bit ADC and an 8 bit ADC to construct the Subranging A/D system and then make a simulation by QuartusII. The result of the experiment shows that the system's sampling rates is 17 MHz, and the resolution is 16 bit, so it can solve an antinomy between sampling rates and resolution, which is prevalent in current market.

Published in:

Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on

Date of Conference:

Aug. 16 2007-July 18 2007