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Hardware Design of a High Performance Multi-Channel High Speed Signal Acquisition and Processing System

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2 Author(s)
Wu Qiang ; DSP and Embedded System Lab, Beijing University of Technology, Beijing 100022 China ; Bai Yangong

This paper describes the hardware design of a high speed acquisition system based on a single DSP of ADI Blackfin family. In order to realize multi-functions in a single board, CPLD and FPGA chips are integrated in this system. This study discusses several main problems during hardware design of this system, such as sampling of multi-channel analog signals, multi-channel digital signals and communication with host board by extended PCI bus, in addition talking about several points concerned with signal integrity issues. The main aim of this research is to demonstrate that as development of DSP and semiconductor techniques, a more complex electric system can be realized on a single DSP.

Published in:

Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on

Date of Conference:

Aug. 16 2007-July 18 2007