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In CMOS circuits, sub-threshold leakage (ISUB) has been an important issue during IC design. As technology keeps on scaling down, new leakage mechanisms such as bound to bound leakage (IBTBT) and gate tunneling leakage (IGATE) can't still be neglected. Estimating the total leakage of a circuit at high level can help the designers to decide whether the design is eligible or should be modified. This paper introduced the main leakage mechanisms, including ISUB, IBTBT and IGATE. The authors have also proposed a method to estimate the average leakage quickly based on pre-characterizing standard cell with BSIM models considering the new mechanisms. The results obtained by experiment on ISCAS benchmark circuits show that the method can be used to get the total leakage value and give a early direction for IC design.