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Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement

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5 Author(s)

Power integrity is a crucial design issue for nano-meter technologies because of decreased supply voltage and increased current. We focused on gate delay variation caused by power/ground noise, and developed a full-chip simulation current model with capacitance and a variable resistor to accurately model current dependency on voltage drop. Measurement results for 90-nm technology are well reproduced in simulation. The error of average supply voltage is 0.9% in average. Measurement results also demonstrate that gate delay depends on average voltage drop.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:54 ,  Issue: 10 )