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Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process

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4 Author(s)
Bergeret, E. ; Univ. Polytech. Sch. of Marseilles, Marseilles ; Gaubert, J. ; Pannier, P. ; Gaultier, J.M.

Modeling and design of CMOS ultra-high-frequency (UHF) voltage multipliers are presented. These circuits recover power from incident radio frequency (RF) signal and supply battery less UHF RF identification (RFID) transponders. An analytical model of CMOS UHF voltage multipliers is developed. It permits to determine the main design parameters in order to improve multiplier performance. The design of this kind of circuits is then greatly simplified and simulation time is reduced. Thanks to this model, a voltage multiplier is designed and implemented in a low-cost electrically erasable programmable read-only memory compatible CMOS process without Schottky diodes layers. Measurements results show communication ranges up to 5 m in the U.S. standard.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 10 )

Date of Publication:

Oct. 2007

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