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Verilog Transformation for an RTL SAT Solver in Formal Verification

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4 Author(s)
Xiaoqing Yang ; Tsinghua Univ., Beijing ; Jinian Bian ; Shujun Deng ; Yanni Zhao

This paper presents a new method automatically translating the Verilog model to an RTL circuit model which can be used in a state-of-the-art finite-domain satisfiability solver EHSAT to check the verified properties. Different methods are used in the transformations of different data types and expressions of Verilog model. Effective backfilling technology is applied in the processes of if...else and case blocks. Experimental results show that this method can make the transformation effective.

Published in:

Communications, Circuits and Systems, 2007. ICCCAS 2007. International Conference on

Date of Conference:

11-13 July 2007