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Power-Gating Adiabatic Flip-Flops and Sequential Logic Circuits

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3 Author(s)
Jianping Hu ; Ningbo Univ., Ningbo ; Dong Zhou ; Ling Wang

In this paper, adiabatic flip-flops with data-retention function are proposed, and a power-gating scheme for adiabatic sequential circuits is presented. The proposed data-retention flip-flops are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The active enable and refresh enable terminals are added for the power-gating operation of the flip-flops. The flip-flops work in three modes. In active mode, the flip-flops act as usual. In hold mode, the flip-flops hold their state on the internal nodes. In refresh mode, the internal nodes are refreshed with their storage value by enabling power-clocks. The energy dissipation of power-gating adiabatic sequential circuits is investigated for different frequencies using a 10times10 adiabatic counter. SPICE simulations show that energy loss of the adiabatic sequential circuits is reduced greatly by using power-gating techniques.

Published in:

Communications, Circuits and Systems, 2007. ICCCAS 2007. International Conference on

Date of Conference:

11-13 July 2007

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